Real EDA pipeline · Testbenches · CDC + RDC analysis · sky130 · GF180 · IHP · No install

From RTL source to

Multi-file SystemVerilog & VHDL synthesis · Live gate-level schematics · Auto-detected testbenches · Real-time code & waveform cross-probing · Structural CDC + RDC hazard analysis · Real Liberty-table STA on sky130, GF180 & IHP · One-click WebSerial FPGA flashing · Zero install

Free · Open-source · Runs on Yosys + GHDL + nextpnr + Icarus + Verilator + ELK

▷ Launch RTL Bench

audio_soc_top.sv ⇄ hybrid → flat → timing analysis

module audio_soc_top (
  input logic clk, rst_n,
  output logic audio_out,
  output logic [7:0] gpio_pins
);
  // Hierarchy → flattened netlist
  // → gate-level timing analysis
  cpu_top     u_cpu       (.clk(clk));
  axi_router   u_bus_router (.m_axi(...));
  audio_pwm    u_audio     (.sample(...));
  apb_decoder u_apb_dec   (.pclk(clk));
endmodule

Why I built this

Digital design shouldn't need
a 20 GB install and a $10,000 license.

I kept watching people who wanted to learn Verilog hit the same wall: the tool needed to see their logic was harder to install than the logic itself. So I built RTL Bench — a browser-based EDA workbench that compiles, simulates, and times real RTL against open-source process libraries, with zero setup.

It runs on Yosys, Icarus Verilog, and Eclipse Layout Kernel — the same open tools professional flows are built on — and it runs entirely on free-tier infrastructure. If you can open a URL, you can design a chip.

— Raghavan, creator of RTL Bench

Who it's for

Built for three kinds of people

🎓

Students & self-learners

Learn RTL without fighting toolchains. Paste SystemVerilog, see it turn into gates, run an auto-generated testbench, watch the waveform — all before your first coffee. Upload a real TB when you're ready for rigor.

⚙️

Hardware engineers

Quick sanity checks on a module you're working on. Real sky130, GF180, and IHP SG13G2 cell timing, per-cell critical-path breakdown, structural CDC + RDC analysis, and vector SVG export for design reviews.

🧪

Researchers & educators

Share a link instead of a repo. Every design loads a live synthesis, STA report, CDC + RDC verification, and waveform — reproducible from any browser, no lab setup required.

3 View Modes

Simple · Hybrid · Detailed — auto-switched by zoom level

RTL → Silicon

Synthesis · simulation · timing · FPGA bitstreams

Real PDK Timing

SkyWater 130 nm · GF180MCU 180 nm · IHP SG13G2 · per-cell Liberty

RTL → FPGA

Tang Nano 9K · 20K · iCE40 UP5K · one-click bitstreams

Compare to X

What makes RTL Bench different

Most browser EDA tools either show you a diagram or run a simulation. RTL Bench does the whole pipeline — synthesis, simulation, waveform, and real-process timing — in one place, for free.

Feature	EDA Playground	HDLBits	DigitalJS	RTL Bench
Multi-file RTL projects	✓	—	—	✓
Interactive gate schematic	—	—	Basic	✓ Hybrid · Flat
SystemVerilog & VHDL support	Verilog only	Subset	—	✓ Both
Clock Domain Crossing (CDC) checks	—	—	—	✓ Structural audit
Reset Domain Crossing (RDC) checks	—	—	—	✓ Structural audit
Real PDK timing (sky130 / GF180 / IHP)	—	—	—	✓
Gate-level STA report	—	—	—	✓
Auto-generated testbenches	—	—	—	✓
User-supplied testbenches (tb_*.sv)	Manual	—	—	✓ Auto-detected
Dual-engine simulation (Icarus + Verilator)	Verilog only	—	—	✓ Auto-routed
Click-to-trace nets	—	—	✓	✓
No account required	—	✓	✓	✓
FPGA bitstream generation	—	—	—	✓ Tang Nano · iCE40
Free to use	✓	✓	✓	✓

Note: Each tool has its own strengths — EDA Playground for simulator breadth, HDLBits for guided practice, DigitalJS for teaching digital logic. RTL Bench focuses on the synthesis-to-timing pipeline those tools don't cover, and adds Verilator-class simulation speed on top of it.

Honest about our limits

What this tool is — and isn't

RTL Bench runs on free-tier infrastructure and open-source tools. That means we're extremely fast for focused RTL work, but we're not built for million-gate chips. Here's the honest breakdown.

✅

Where RTL Bench shines

Module-level designs — CPU blocks, ALUs, FSMs, protocol decoders
Multi-file SystemVerilog / VHDL projects with hierarchy
Cross-probing & visualization for learning, reviews, and teaching
Real PDK timing on sky130, GF180, and IHP — per-cell Liberty arcs
CDC & RDC verification for clock/reset domain crossings
Quick FPGA prototyping on Tang Nano and iCE40 boards

⚠️

Where it has hard limits

~500 KB per file, 1 MB total per project (keeps servers free)
~1,500 gates before the schematic renderer lags — use Block view
5,000 cells maximum for flat STA — pick a sub-module instead
No UVM, classes, or structs — simulator expects synthesizable Verilog
Session-only storage — your code is lost if you close the tab
Not a tape-out flow — no place-and-route or GDSII generation

▷ Open RTL Bench — try it free

Engineered for real RTL workflows

Not a diagram toy — every feature maps to a step in an actual synthesis and timing-signoff pipeline.

📁

Multi-file SystemVerilog & VHDL projects

Drop a folder of .sv, .v, or .vhd sources and data files; relative paths are preserved so $readmemh finds its files. Top modules and entities are auto-detected.

🧩

Hierarchy-preserving synthesis

Submodule instances render as encapsulated blocks with named port pins and input/output direction dots. Toggle Hierarchy to collapse into blocks, or Flat to unroll every gate — from the same compile.

⏱

Gate-level static timing analysis

Yosys techmap decomposes the design to real gates, then the longest structural path is measured as gate depth. Per-process-node conversion (180/90/45/7 nm) gives a nanosecond estimate with top-K critical paths and a cell-by-cell breakdown.

🔍

Bidirectional cross-probing

Double-click any identifier in the code to highlight its gates on the schematic and dim non-target waveform traces to 18% opacity. Inspect data flows from source line to digital waveform seamlessly.

🛡️

Structural Clock Domain Crossing (CDC)

Topological back-tracing inspects every register clock boundary. Flags combinational hazards and missing synchronizers while verifying multi-stage flip-flop synchronizer chains. Full report page with a domain interaction matrix and per-path diagnostics.

🔁

Reset Domain Crossing (RDC) analysis

Structural RDC detection across reset boundaries — catches the same-clock / different-reset bugs that CDC tools miss. Traces reset nets back to their source, verifies 2-FF reset synchronizer chains, and flags combinational reset generators and soft resets before tape-out.

🚀

Dual-engine simulation: Icarus + Verilator

Small designs run instantly on Icarus Verilog. Designs past ~30,000 cells are routed to Verilator for C++-compiled speed, with automatic Icarus fallback if Verilator can't finish. The engine, mode, and reason are always visible in the waveform drawer.

⚡

FPGA synthesis & WebSerial flashing

Go from RTL to physical silicon without terminal tools. Compiles with Yosys and nextpnr, auto-recovers from pin conflicts, and streams bitstreams directly to Tang Nano and iCE40 boards via WebSerial.

📈

Bring your own testbench — or auto-generate one

Drop tb_yourdesign.sv next to your design and RTL Bench auto-detects it by filename or $dumpvars signature. The testbench is excluded from synthesis, STA, and FPGA builds but runs in simulation. No TB? It reads your top module's ports with Yosys and generates one: reset release, 60 random stimulus cycles, drain. Waveforms appear in the built-in drawer either way.

🧵

Vector bus collapsing

Bit-blasted Yosys nets are regrouped into single vector wires with IEEE /W slash notation and a width label. Branch fan-out is drawn with proper solder dots, so wide datapaths stay legible.

🔗

Fused constant comparators

An == against a literal like 8'hA5 is rendered as a single comparator cell with the value fused into an adjacent chip. No dangling constant wires — the operation reads as one unit.

🖱️

Click-to-trace nets

Every wire is interactive. Click any net to highlight the full routed path across the canvas — from a primary input through combinational logic to a register or output pin. Ideal for tracking feedback loops.

RTL to waveform, in five stages

The pipeline below runs on every compile and simulate — the same flow your commercial toolchain uses.

Upload or paste your RTL

Drop a folder of sources, paste a single file, or pick a preset. Top module and data files are auto-detected.

Yosys RTLIL elaboration

Your source is sandboxed and elaborated by read_verilog → proc → opt → clean. Clocks and resets are inferred automatically.

ELK placement & routing

Eclipse Layout Kernel positions cells in a LEFT→RIGHT layered graph and routes every net with orthogonal Manhattan edges.

Inspect & trace

Zoom through the hierarchy, click nets to trace them, and export the current view as a clean vector SVG.

Simulate & inspect

Run an auto-generated testbench, watch signals toggle in the waveform drawer, and verify behaviour before sign-off.