Why this exists
Learning digital design shouldn't require a 20 GB install, a $10,000 license, or a weekend spent fighting toolchain paths. Yet that's the reality for most students and hobbyists who want to see what their Verilog actually does.
RTL Bench was built to fix that. Paste your code, click a button, and watch it transform — from source, to elaborated netlist, to placed-and-routed schematic, to simulated waveform, to a static timing report. All in a browser tab. Small designs finish in seconds; large ones compile to native simulation code.
Why I built this
I was working on multiple projects at the same time and honestly kept forgetting the key details of my own circuits. Every time I had to revisit an older design, I was literally going line by line through the code just to remember how it worked.
I tried using AI, but it doesn't always tell you what’s actually there in the hardware. I looked into some well-known open source tools too, but none gave me what I wanted: just 3 to 5 minutes to glance at the schematic, trace paths, and refresh my memory without a heavy setup.
How it came together
So I went through documentation of open-source and commercial tools and built a minimal version of this just for myself.
I used it in my interviews and whenever I had to explain my projects to someone, and it worked really well. Then a friend of mine had the exact same issue, so I shared it with him and he found it super useful too.
That’s when I thought of just making it open and putting it out there. It’s not a finished product yet — still building and tweaking it every day, but it’s live in the browser.
The open-core model
RTL Bench is partially open source. The frontend — landing page, studio UI, waveform viewer, schematic renderer, STA report — is public on GitHub under the MIT license. The backend — Yosys orchestration, dynamic testbench generation, static timing analysis algorithms — is proprietary and closed.
This split isn't arbitrary. The frontend is where most learning happens: it's readable, forkable, and easy to reason about. The backend is where months of iteration produced the specific pass sequences, port-probing logic, and stimulus heuristics that make the tool robust against arbitrary user code. That work stays protected.
Open — MIT licensed
- Landing page & About page
- Studio UI shell & editor
- Schematic renderer (ELK + SVG)
- Waveform viewer (VCD → canvas)
- STA report viewer
- Vector SVG export
Proprietary
- Yosys orchestration pipeline
- Dynamic testbench generation
- Port probing & clk/rst detection
- SV→Verilog conversion logic
- Dual-engine Icarus / Verilator routing
- Gate-level STA algorithm
- CDC + RDC structural analyzers
The tools that make it work
RTL Bench stands on the shoulders of excellent open-source projects. Here's what's running behind the scenes:
Every compile, in five stages
Whether you're pasting a single module or uploading a 30-file SoC, the flow is the same. Each stage runs in isolation, so a syntax error in one file doesn't cascade into a wall of confusing messages.
1. Upload — Drop a folder or paste a file. Top module is auto-detected
or overridden from a dropdown.
2. Elaborate — Yosys parses SystemVerilog, runs proc,
opt, and clean, then writes a JSON netlist.
3. Place & route — Eclipse Layout Kernel positions cells in a
layered LEFT→RIGHT graph with clean orthogonal routing.
4. Simulate — A testbench is auto-generated from the probed port list;
small designs run on Icarus Verilog, large ones route to Verilator for compiled speed. VCD output is identical either way.
5. Analyze — On-demand STA decomposes the design with
techmap and reports gate depth, critical path, and per-node timing.
What's next
tb_*.sv files by name or $dumpvars signature. Excludes them from synthesis, STA, and FPGA builds, but runs them in simulation. Generates a starter TB when none is supplied.Built by
Try RTL Bench
No signup, no install, no credit card. Just open the studio and paste your first module.