Terms of Service & Conditions of Use

Document Ref: TOS-RTL-2026 · Effective Date: October 4, 2026 · Independent Developer Platform

Please read these Terms of Service and Conditions of Use (“Terms”) carefully before accessing or using RTL Bench (“rtlbench.com”, “we”, “us”, or “our”), an independent Electronic Design Automation (EDA) project and digital hardware engineering platform maintained by its creator.

By accessing the platform, running compilations, inspecting schematics, or using hardware flashing tools, you agree to these Terms. If you do not agree, please discontinue use of the service.

1. The Platform & Scope of Service

RTL Bench provides a zero-install, cloud-assisted digital logic development environment for synthesizing, simulating, inspecting, timing, and deploying Hardware Description Languages (Verilog, SystemVerilog, and VHDL).

The platform runs on shared compute infrastructure. We reserve the right to modify toolchains, update process models, impose concurrency locks, or adjust timeout parameters at any time to preserve shared server availability.

2. Intellectual Property & Your Code

2.1 Complete User Ownership

You retain 100% full ownership, copyright, and patent rights over any hardware design, RTL code, testbench, or constraint file you write or upload to RTL Bench. We claim zero ownership or commercial rights over your code.

2.2 Ephemeral Processing Only

To synthesize and visualize your designs, our cloud runners ingest and process your source code inside temporary, isolated workspaces. We do not claim rights to your IP, license your designs, sell your files to third parties, or use private code to train commercial machine learning models.

3. Acceptable Use Policy

RTL Bench is provided for digital engineering, learning, research, and design iteration. You agree not to:

Submit designs or scripts engineered to cause infinite loops, memory crashes, or denial-of-service on server runners;
Abuse our compilation backend for cryptocurrency mining or non-EDA computing workloads;
Attempt to probe, breach, or exploit the containerized sandboxes or server infrastructure;
Bypass or spoof automated rate limiters or compilation queue concurrency locks.

4. Pre-Silicon Engineering & Timing Disclaimers

THE PLATFORM, TIMING REPORTS, WAVEFORMS, AND SCHEMATICS ARE PROVIDED ON AN “AS IS” AND “AS AVAILABLE” BASIS WITHOUT WARRANTIES OF ANY KIND.

The Static Timing Analysis (STA), gate-depth metrics, Clock Domain Crossing (CDC) checks, and cell delay lookups provided across SkyWater 130nm, GlobalFoundries 180nm, and IHP SG13G2 are architectural estimations intended for prototyping and educational evaluation.

Not for Silicon Sign-Off: Nominal standard-cell Liberty lookups do not account for physical placement, clock tree jitter, multi-corner variation (MMMC), or post-route wire parasitics (SPEF). RTL Bench does not guarantee silicon tape-out success or functional hardware closure. The maintainer is not liable for wafer manufacturing failures or mask NRE expenses.

5. Physical Hardware & WebSerial Flashing

RTL Bench enables direct in-browser FPGA programming for boards such as the Sipeed Tang Nano 9K, Tang Nano 20K, and Lattice iCE40UP5K via the WebSerial API.

Pin Configuration: You are solely responsible for ensuring assigned pins in your constraint files match appropriate I/O voltages and hardware peripherals.
Hardware Safety: While RTL Bench implements software guards to filter known reserved JTAG and flash lines, the platform maintainer accepts no liability for physical board damage, burned I/O pads, electrical overstress, or port damage resulting from hardware deployment.

6. Third-Party Trademarks & Fair Use

All third-party product names, logos, and brands mentioned across RTL Bench documentation and comparison pages—including but not limited to EDA Playground, ChipVerify, DigitalJS, Synopsys, Cadence, Siemens EDA, AMD Vivado, Intel Quartus, Lattice, and Gowin—belong strictly to their respective owners.

Their reference on this site is strictly for factual identification and nominative fair-use comparative analysis. RTL Bench is an independent engineering project and is not affiliated with, endorsed by, or sponsored by any of these entities.

7. Limitation of Liability

TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL THE MAINTAINER OF RTL BENCH BE LIABLE FOR ANY INDIRECT, INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES (INCLUDING LOSS OF DATA, PROFITS, OR PROJECT TIMELINES) ARISING OUT OF THE USE OR INABILITY TO USE THIS SERVICE.

8. Changes to These Terms

We may occasionally update these Terms to reflect toolchain additions or server changes. Continued use of the platform following updates constitutes agreement with the revised Terms.