Learn RTL Bench

A visual tour of every feature. Each section pairs a short explanation with an animated demo of the exact interaction you'll see in the workbench — no screenshots to guess at, no GIFs to sit through.

1. What is RTL Bench?

RTL Bench is a browser-based workbench for small- to medium-sized digital designs. You write Verilog, SystemVerilog, or VHDL on the left; a live toolchain on the right elaborates, draws, simulates, and analyses your circuit as you type.

Elaborates your source with Yosys (Verilog) or GHDL (VHDL) — one file or twenty.
Draws a schematic from the block level down to individual gates.
Simulates the design and renders inspectable waveforms.
Estimates timing against a standard-cell library (sky130, gf180, or IHP SG13G2).

💡 Fastest way in: open the Examples menu in the top bar and click RISC-V 32-bit ALU (multi-file). It exercises every feature in one go.

2. Writing HDL

The editor accepts SystemVerilog (.sv), Verilog (.v), and VHDL (.vhd / .vhdl). Pick the language from the dropdown in the top bar; it changes how the backend parses your source.

A minimal module

module counter (
    input  logic       clk,
    input  logic       rst_n,
    output logic [7:0] q
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) q <= 8'h00;
        else        q <= q + 8'd1;
    end
endmodule

→ Working in VHDL? Read the VHDL guide

Code ↔ diagram link

The two panes are linked bidirectionally. Hover a line of code — the corresponding node lights up on the right. Hover a node — the source range is selected in the editor.

studio — hover link

logic [31:0] add_out;
logic [31:0] logic_out;
logic [31:0] slt_out;
                

Hovering a declaration highlights its node — and vice versa.

3. Multi-file projects

Use the 📎 Files or 📁 Folder button to upload one or more HDL files. RTL Bench merges them into a single compilation unit — the top module is detected automatically from every file.

studio — upload folder

rv32_alu_top.sv

adder_sub.sv

logic_ops.sv

// rv32_alu_top.sv module rv32_alu_top (...); adder_sub u_adder (...); logic_ops u_logic (...); endmodule

// adder_sub.sv module adder_sub (...); assign b_xor = b ^ {32{op}}; assign y = a + b_xor + op; endmodule

// logic_ops.sv module logic_ops (...); case (sel) 3'b100: y = a ^ b; 3'b110: y = a | b; endcase

// ...switching files...

Upload a folder → chips appear automatically → editor cycles through files → the top module is chosen for you.

Hierarchy vs. Flat

Mode	What you see	When to use
Hierarchy	Each instantiated submodule is a labelled box with ports.	Default. Preserves design intent, stays fast on large designs.
Flat	Every submodule unrolled to primitive gates.	Only when you need to see inside one submodule.

⚠ Flattening a design with many multipliers (20+) will freeze the browser while ELK lays out the graph. RTL Bench asks first — heed the warning.

4. Block / Hybrid / Gate views

Three buttons in the top bar — and a floating bar in fullscreen — control how much detail the schematic shows.

studio — view modes

// Same design, // three ways to // look at it. Block → high-level Hybrid → auto-switch Gate → every gate

Block view

Hybrid

Gate view

Block → Hybrid → Gate. Hybrid switches between the two automatically based on zoom level.

5. Navigating the schematic

Pan, zoom, fit

Pan — click and drag anywhere on the canvas.
Zoom — scroll wheel, or pinch on a trackpad.
Fit to view — the ⌖ button top-right.
Fullscreen — the ⤢ button next to it.

Inspecting signals

Click a wire to select it. Selected nets stay highlighted in blue.
Buses render as thick grey lines with a width badge (32, [31:0]) at branch points.
Submodules appear as yellow dashed rectangles with green (input) and blue (output) ports.

💡 In Hybrid mode, zoom is what flips between views: below about 0.75× you see blocks, above that the gate-level detail appears. If a view feels "wrong", try scrolling a notch.

6. Simulation & waveforms

Click Waves in the bottom status bar to open the simulation drawer, or press ▶ Run Testbench inside it. RTL Bench generates a simple stimulus, runs the design, and streams back a VCD waveform.

studio — waveform measurement

clk 1
data_in 0x30
match_flag 0
counter 0x25

Click once for cursor A, again for cursor B. The header shows Δ and the derived frequency — perfect for measuring clock periods.

All cursor gestures

Gesture	Action
Click the waveform	Places A, then B, then moves the nearer of the two.
Drag a cursor	Slides it; snaps to the nearest transition.
`Shift` + drag	Free positioning, no snap.
Hover anywhere	Shows a blue hover cursor and live values in the sidebar.
Right-click	Clears both cursors.

Resize and maximise

Drag the horizontal bar at the top of the drawer to resize it.
Click the 🗖 icon to maximise the drawer.
The code editor reserves space automatically — the last lines of your source stay visible above the drawer.

7. Timing analysis (STA)

Click ⏱ Calculate STA in the bottom bar. RTL Bench synthesises your design, maps it to standard cells from the selected PDK, walks the critical path, and reports the worst-case delay.

studio — status bar (STA cycle)

⏱ Calculate STA

Critical: 3.42 ns · Slack: +6.58 ns · 100 MHz

Idle → calculating → done. Green means positive slack; yellow is marginal; red is a violation.

What you get

Critical path delay in nanoseconds — the longest combinational path.
Slack against a 10 ns clock period (100 MHz). Negative = violation.
A status chip that turns green, yellow, or red depending on slack.

Click the coloured chip after STA runs. The /sta page breaks down every stage, shows cell counts by type, and lets you re-run with a different target node (sky130, gf180, ihp).

⚠️ STA flattens the design. If it has many multipliers (15+) or a flattened netlist over 50k gates, the backend will time out. Analyse one module at a time using the Top-module dropdown.

8. Fullscreen & the mode bar

Click ⤢ on the canvas to enter fullscreen. The controls enlarge for easier clicking, and a small bar appears at the top-center of the screen letting you switch view modes without leaving fullscreen.

studio — fullscreen toggle

module rv32_alu_top ( input [31:0] a, b, input [3:0] alu_op, output [31:0] result );

Fullscreen enlarges the controls and slides in the mode bar. Esc exits.

Try it in the real studio

Click ⤢. The canvas expands to fill the screen.
The mode bar appears top-center with Block view / Hybrid / Gate view.
Click any mode — the diagram switches instantly, the bar stays.
Press Esc or click ✕ to return.

9. Gestures & shortcuts

studio — splitter drag

module ...

Drag the thin vertical bar between editor and canvas. Double-click it to reset to 40 / 60.

Global

Key / gesture	Action
`Ctrl`/`Cmd` + `Enter`	Force re-generate the schematic
`Esc`	Exit fullscreen / close modals

Schematic

Gesture	Action
Click + drag	Pan
Scroll / pinch	Zoom
Click a wire	Select / deselect the net

Waveform

Gesture	Action
Click	Place / move cursor A or B
Drag a cursor	Slide, snaps to nearest edge
`Shift` + drag	Free positioning, no snap
Right-click	Clear cursors

10. Troubleshooting

Nothing appears in the schematic

Check the error modal — a syntax error blocks elaboration.
Confirm the top module in the TOP: dropdown.
Press Generate to force a fresh compile.

Simulation shows no signals

Open the browser console (F12) — a red error usually explains it.
If it says fileModules: [] with files loaded, reload to reset state.

STA times out

Pick a single module from the Top-module dropdown first.
Designs with many multipliers should be analysed one submodule at a time.

Editor's last lines are hidden

The drawer reserves space automatically — close and reopen it if it doesn't.
Or drag the drawer's top bar down to reduce its height.

Open the workbench →

Frequently asked questions

What is RTL Bench and who is it designed for?

RTL Bench is a cloud-based development environment for digital design engineers, students, and hobbyists. It offers instant Verilog and VHDL simulation, interactive schematic generation, open-source static timing analysis, and hardware FPGA programming.

Do I need to create an account or install plugins to use RTL Bench?

No. RTL Bench is zero-install and requires no login to start writing and testing HDL code. Everything runs directly in modern web browsers.

Which FPGA hardware can I program directly from the browser?

Using the WebSerial API in Chromium-based browsers (Chrome, Edge), you can program boards like the Sipeed Tang Nano 9K/20K and Lattice iCE40 without installing local programmer drivers.

Verilog & SystemVerilog Master module declarations, procedural logic, and synthesis coding styles.
VHDL in the browser Write IEEE 1076-2008 compliant entities and architectures.
Simulation & waveforms Run auto-generated testbenches and inspect live VCD waveforms.

Try it in the workbench →

1. What is RTL Bench?

2. Writing HDL

A minimal module

Code ↔ diagram link

3. Multi-file projects

Hierarchy vs. Flat

4. Block / Hybrid / Gate views

5. Navigating the schematic

Pan, zoom, fit

Inspecting signals

6. Simulation & waveforms

All cursor gestures

Resize and maximise

7. Timing analysis (STA)

What you get

8. Fullscreen & the mode bar

Try it in the real studio

9. Gestures & shortcuts

Global

Schematic

Waveform

10. Troubleshooting

Nothing appears in the schematic

Simulation shows no signals

STA times out

Editor's last lines are hidden

Frequently asked questions

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