The schematic & view modes
Every time you click Generate, RTL Bench draws a schematic of your design. It shows structure, connectivity, and hierarchy — from a single top-level block down to individual logic gates, depending on how much detail you ask for.
Three views, one canvas
Three buttons in the top bar — Block, Hybrid, and Gate — control how much detail the schematic shows. The design does not change; only the level of abstraction does.
Block view
The whole design collapses into one rectangle. Ports on the left are inputs (green), ports on the right are outputs (blue). Useful when you are looking at a single module as a black box, or when you want to see the boundary of the current top without any internal detail.
Gate view
Every instantiated submodule is flattened and every primitive cell is
drawn — $dff, $add, $mux,
$xor, and so on. This is the closest view to what a
synthesizer sees.
The labels are Yosys's cell types with the leading $
stripped. Cells whose names contain recognisable patterns are drawn
with friendly labels (+ for add,
MUX for mux, and so on).
Hybrid
This is the default and the one most users end up in. Each instantiated submodule stays as a labelled box with its ports, but the top-level logic between them is shown as gates. You see the hierarchy and the connectivity at the same time.
Code ↔ diagram linking
The editor and the schematic are linked bidirectionally. Hover a line of Verilog or VHDL in the source and the corresponding node on the right lights up. Hover a node and the corresponding source range is highlighted in the editor.
The link is built during elaboration — Yosys records the source location of every signal and cell it creates, and RTL Bench maps those back to character offsets in your file.
The link only works when the file that declared a signal is the one currently shown in the editor. If your design spans multiple files, clicking a node opens the file where the signal was declared.
Navigating the canvas
Pan and zoom
- Pan — click and drag anywhere on the canvas.
- Zoom — scroll wheel, or pinch on a trackpad.
- Fit to view — the
⌖button in the top-right corner. Zooms out so the entire design is visible. - Fullscreen — the
⤢button next to it. Expands the canvas to fill the browser window.
Selecting wires
Click any wire to select the net it carries. Selected nets stay highlighted in blue across the canvas, which is the fastest way to trace a signal through a complex design.
Buses — multi-bit nets — are drawn thicker than single-bit wires and
carry a width badge at branch points (32 or
[31:0]).
What the boxes mean
| Shape | What it is |
|---|---|
| Green ports (left side) | Module inputs. Fan-in from the outside world. |
| Blue ports (right side) | Module outputs. Fan-out to the outside world. |
| Yellow dashed rectangle | An instantiated submodule. The name inside is the instance name (like u_adder), and the smaller label under it is the module type it instantiates. |
| Solid grey rectangle | A primitive cell from Yosys — a logic gate, mux, adder, or flip-flop. Only appears in Hybrid and Gate views. |
| Circle with a symbol | An arithmetic operator (+, −, ×) or comparison (==, <, >). |
Comparing block and gate views on the same design
Flip between Block and Gate on a design with submodules and you see why both modes matter. Block shows you what the module does; gate view shows you how it does it. Hybrid is the middle ground — a top-level view that shows hierarchy but drops into gates where the interesting logic lives.
Resizing the panes
The editor and the schematic share the screen. Drag the vertical splitter between them to give more room to whichever side you need. Double-click the splitter to reset the ratio to 40 / 60.
Keyboard shortcuts
| Key | Action |
|---|---|
| Ctrl / Cmd + Enter | Force re-generate the schematic from the current editor contents. |
| Esc | Exit fullscreen, close modals. |
There is no keyboard shortcut to switch between Block, Hybrid, and Gate. Click the buttons.
Frequently asked questions
RTL Bench uses Yosys to elaborate your HDL into an abstract syntax tree and RTL Intermediate Language (RTLIL). It converts coarse-grained modules and fine-grained logic cells into an interactive visual graph using the Eclipse Layout Kernel (ELK) in the browser.
Yes. Clicking any cell, flip-flop, or multiplexer in the schematic highlights the corresponding source code lines in the editor, making it easy to see how HDL expressions map into physical hardware.
The RTL schematic preserves coarse-grained operations like word-level adders, multiplexers, and state machine registers. The gate-level schematic shows the mapped standard cells (NAND, NOR, DFF) after technology mapping against a specific foundry PDK or FPGA target.