Active-low reset: why rst_n is everywhere

Almost every digital design has a reset. Almost every reset is named rst_n, rst_l, or reset_b — with a lowercase letter that quietly encodes the polarity. Miss it and your simulation never leaves reset.

The short version

An active-low reset asserts when the signal is 0 and deasserts when it is 1. It is the opposite of an active-high reset, which asserts on 1.

The suffix on the port name tells you which one you have. These suffixes all mean "active-low":

There's no universal standard. Every company picks a convention. What matters is that the same convention is used consistently — and that the simulator agrees with you.

Why active-low is so common

Three practical reasons, in order of how often they come up:

1. Transistors historically reset more reliably to ground. An N-channel pull-down to 0 was the natural way to force a node low in older process nodes. That physical habit became a naming convention that outlived the reason.
2. Board-level resets are usually open-drain. A supervisor IC pulls the reset line low when power is bad and lets it float high when power is good. The signal is naturally active-low at the pin.
3. It's a single-character suffix. rst_n is shorter than reset_negated or reset_active_low, and it fits in a port list without wrapping.

How RTL Bench detects polarity

RTL Bench looks at the port name. If it ends with _n, _l, _b, or starts with n_, it treats the port as active-low. Otherwise, a port whose name contains rst or reset is treated as active-high.

The detection matters when you click ▶ Run Testbench. The auto-generated stimulus holds the reset in its asserted state for the first few cycles, then releases it. Active-low gets held at 0; active-high gets held at 1.

module counter (
    input  logic       clk,
    input  logic       rst_n,   // → driven low for the first 12ns
    output logic [7:0] q
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) q <= 8'h00;
        else        q <= q + 8'd1;
    end
endmodule

If you swap rst_n for rst in the same design, the auto-testbench holds the signal at 1 for the first few cycles, then releases it to 0. The waveform changes accordingly — no code changes required.

What to do instead of renaming

If you cannot rename the port — because it is part of a legacy interface, or the name is defined in a spec you have to match — write your own testbench. RTL Bench will use it verbatim, and you control exactly how the reset signal is driven.

module tb;
    logic        clk = 0;
    logic        por_ok = 0;   // active-low reset, custom name
    logic [7:0]  q;

    counter dut (.clk(clk), .por_ok(por_ok), .q(q));

    always #5 clk = ~clk;

    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, tb);
        #20  por_ok = 1;    // release reset
        #500 $finish;
    end
endmodule

See Simulation & waveforms for the full testbench guide, including the $dumpfile and $dumpvars requirements.

Which convention should you use?

Use rst_n unless you have a reason not to.

• It is the most common in open-source RTL and modern ASIC design.
• RTL Bench and most linters recognise it automatically.
• It sorts naturally in editor autocomplete.
• It is unambiguous — nobody has to look at a comment to know the polarity.

If your team already uses reset_b or rst_l, stay consistent with the team. Consistency beats correctness when they conflict.

Frequently asked questions