VLSI & RTL concepts — a reference

The terms that show up in RTL design, synthesis, simulation, and timing analysis. Short definitions in plain English, with links to the deeper pages where they matter.

Design abstraction levels

A digital design can be described at several levels of detail. Every level below is a valid representation of the same chip — just at different resolution.

Register Transfer Level RTL

An abstraction where a design is described as data moving between registers under the control of a clock. RTL describes what happens on each cycle — read a register, do some arithmetic, write the result back — without specifying the gates that implement it. Verilog and VHDL are the two languages used to write RTL.

Behavioural model

Any description that specifies what a design does without prescribing how it is built. RTL is a behavioural model. So is a testbench, or a high-level algorithm written in SystemVerilog.

Gate level netlist

A description of the design as a network of logic gates and flip-flops. A netlist lists every cell and the wires between them. Synthesis produces a gate-level netlist from RTL.

Transistor level schematic

A description of the design as a network of transistors. Used in custom analog and memory design. Not something RTL tools deal with.

Storage & sequential logic

Sequential logic has memory. Its output depends on past inputs, not just the current ones. Storage elements are what make a design "sequential" instead of "combinational".

Combinational logic

Logic with no memory. The output is a pure function of the current inputs, and any change on the input propagates to the output after a delay. Adders, multiplexers, and comparators are combinational.

Flip-flop FF, register

An edge-triggered storage element. On the active clock edge, it captures the value on its D input and presents it on its Q output. Between edges, it holds its value regardless of D. Every design with a clock is built on flip-flops. In Verilog, a flip-flop is inferred from always_ff @(posedge clk).

Latch

A level-sensitive storage element. While its enable is asserted it is transparent — Q follows D. When enable is deasserted, it holds the last value. Latches are usually unintentional in RTL because they cause timing-analysis headaches. Yosys warns with "Latch inferred for signal" when it detects one.

Metastability

The state a flip-flop can enter when its D input changes too close to the clock edge. Instead of resolving cleanly to 0 or 1, the output oscillates for a while before settling. Two back-to-back flip-flops (a synchroniser) are the standard defence against metastability across clock domains.

Timing

Timing is the study of whether signals arrive where they need to, when they need to. Static timing analysis checks this without running any simulation.

Setup time

The minimum time a D input must be stable before the clock edge for a flip-flop to capture it correctly. A setup violation means the data arrived too late.

Hold time

The minimum time a D input must remain stable after the clock edge. A hold violation means the data changed too soon after the edge. Hold violations are rare in RTL-only designs but common in physical layouts.

Critical path

The longest combinational path in a design — usually from one flip-flop's Q to the next flip-flop's D. The critical path delay determines the fastest clock the design can run at.

Slack

The margin between a path's actual delay and the constraint it has to meet. Positive slack means the design closes timing. Negative slack means a violation. See Timing analysis →

Path classification

The four standard categories every timing path falls into — in2reg, reg2reg, reg2out, and in2out — based on where the path starts and ends. See STA path types →

Static timing analysis STA

Timing verification that walks every path in a design and reports the worst-case delay. "Static" means it does not run a simulation — it analyses the netlist directly. Fast, exhaustive, and the industry-standard gate before tape-out. See Timing analysis →

Clocks & resets

Almost every synchronous design has a clock and a reset. Their conventions have outsized impact on how a design behaves in simulation.

Clock

A periodic signal that drives every flip-flop in a synchronous design. Every flip-flop captures its input on the same edge, so the whole design advances one step per clock cycle.

Clock domain

A group of flip-flops driven by the same clock. A design with two clocks has two domains. Data crossing between domains needs special handling to avoid metastability.

Clock domain crossing CDC

A path that carries data between two clock domains. CDC paths cannot be checked by normal setup/hold analysis. Standard fixes include two-flop synchronisers for single-bit signals and asynchronous FIFOs for buses.

Reset

A signal that forces a design into a known state — usually all flip-flops to 0. Every synchronous design should have one, so that power-up does not leave registers in random states.

Active-low reset rst_n, reset_b

A reset that asserts when the signal is 0 and deasserts when it is 1. The trailing _n, _l, or _b on the port name marks the polarity. RTL Bench detects this by name. See Active-low reset →

Synchronous reset

A reset that takes effect on the next clock edge. Cleaner for timing analysis but requires a running clock to work.

Asynchronous reset

A reset that takes effect immediately, without waiting for a clock edge. Works even if the clock is not running, but needs careful deassertion to avoid a metastable release.

Tooling

The tools that turn RTL into something a fab can build.

Elaboration

The step that expands parameterised modules, resolves generates, and builds the full hierarchy from your source files. Errors like "module not found" or "port mismatch" show up at elaboration.

Synthesis

The process of converting RTL into a gate-level netlist. A synthesizer reads your Verilog or VHDL, chooses cells from a standard-cell library, and produces a netlist that implements the same behaviour.

Lint

Static analysis that catches common mistakes before synthesis — unused signals, multiple drivers, inferred latches, sensitivity list mismatches. RTL Bench surfaces Yosys lint warnings after each Generate.

Yosys

The open-source synthesis and formal-verification framework used by RTL Bench for Verilog and SystemVerilog. It elaborates, optimises, and techmaps designs to a standard-cell library.

GHDL

The open-source VHDL simulator and synthesis front-end. RTL Bench uses it via the Yosys GHDL plugin to bring VHDL into the same pipeline as Verilog. See VHDL in the browser →

Files & formats

The file types you will encounter in an RTL project.

.v — Verilog

Classic Verilog source. Handled by Yosys with the SystemVerilog parser, so the tool accepts a superset of the language in a .v file. See Verilog guide →

.sv — SystemVerilog

SystemVerilog source. Same backend as .v, but the file extension signals that SystemVerilog features are expected. See Verilog guide →

.vhd, .vhdl — VHDL

VHDL source. Handled by GHDL. See VHDL guide →

.svh, .vh — header files

Header files for `include. Not compiled directly, but available on the include path during elaboration.

.hex, .mem, .dat — memory init

Data files for $readmemh and $readmemb. Uploaded alongside your HDL and copied into the working directory before synthesis. See Multi-file projects →

Standard cell

A pre-designed logic gate, adder, mux, or flip-flop from a technology library. A synthesizer picks standard cells to build your design. The library is a fixed set — you do not design cells yourself unless you are doing custom layout.

Process Design Kit PDK

The package of transistor models, standard cells, design rules, and Liberty files that a fab provides for a process node. RTL Bench supports three: sky130, gf180, and IHP SG13G2. See PDK comparison →

Liberty file .lib

A text file that describes the timing, power, and function of every cell in a standard-cell library. STA reads a Liberty file to know how fast each cell is under a given load.

Value Change Dump VCD

The standard waveform file format. A simulator writes a VCD during simulation, and a waveform viewer reads it back. RTL Bench renders VCDs directly in the browser. See Simulation & waveforms →

Testbench

A module that instantiates your design and drives its inputs. A testbench is not synthesizable — it exists only to exercise the design in simulation. RTL Bench auto-generates one if you do not provide your own. See Simulation & waveforms →

Netlist

A list of every cell in a design and the wires between them. The output of synthesis, the input to placement and routing.

Frequently asked questions