Online VHDL compiler & simulation guide

VHDL is known for strict type safety and structured entity-architecture separation. This guide explains how IEEE 1076-2008 VHDL compiles in the browser using GHDL, how visual schematics are elaborated, and how mixed VHDL/Verilog synthesis works.

1. The VHDL compilation pipeline: GHDL + Yosys

In traditional ASIC and FPGA flows, compiling VHDL requires heavy vendor suites like Vivado, Quartus, or ModelSim. In RTL Bench, VHDL compilation is powered by GHDL (the open-source VHDL analyzer and simulator) coupled directly to Yosys:

• Analysis & Parsing: GHDL parses your source with --std=08 -fsynopsys, checking strict type matches across ieee.std_logic_1164 and ieee.numeric_std.
• Elaboration: The top-level entity and its bound architecture are resolved. Constants, generics, and generate loops are calculated.
• RTLIL Mapping: The ghdl-yosys-plugin converts GHDL's intermediate abstract syntax tree directly into RTLIL (RTL Intermediate Language).
• Schematic & Netlist Generation: Yosys runs logic optimization (opt, clean) and passes the resolved gate-level netlist to both the in-browser schematic renderer and the timing engine.

2. Entity vs. architecture: The separation of interface and logic

Unlike Verilog where module ports and internal logic are declared inside a single block, VHDL enforces strict isolation between interface and implementation:

Synthesizable example: Parameterized binary counter

Here is a complete, synthesizable VHDL-2008 8-bit counter with synchronous clear and load:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_8bit is
  generic (
    WIDTH : natural := 8
  );
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    load  : in  std_logic;
    din   : in  std_logic_vector(WIDTH - 1 downto 0);
    dout  : out std_logic_vector(WIDTH - 1 downto 0)
  );
end entity counter_8bit;

architecture rtl of counter_8bit is
  signal count_reg : unsigned(WIDTH - 1 downto 0);
begin
  process(clk, rst_n)
  begin
    if rst_n = '0' then
      count_reg <= (others => '0');
    elsif rising_edge(clk) then
      if load = '1' then
        count_reg <= unsigned(din);
      else
        count_reg <= count_reg + 1;
      end if;
    end if;
  end process;

  dout <= std_logic_vector(count_reg);
end architecture rtl;

3. Mixed-language synthesis (VHDL + Verilog)

In modern silicon engineering, teams rarely write 100% pure VHDL or 100% pure Verilog. Existing IP blocks (like AXI peripherals or memory controllers) are often written in SystemVerilog, while control pipelines may be written in VHDL.

Because RTL Bench compiles VHDL and Verilog into unified RTLIL intermediate representations:

• You can instantiate a Verilog module inside a VHDL architecture using a matching component declaration.
• You can instantiate a VHDL entity inside a SystemVerilog module simply by matching port names.
• All internal signals crossing language boundaries automatically preserve their bus widths and data types.

4. Common VHDL pitfalls & fixes

1. Mixing std_logic_vector with Arithmetic:
   You cannot directly add + 1 to a std_logic_vector. Always import ieee.numeric_std and cast the vector to unsigned or signed before applying arithmetic operators.
2. Signals vs. Variables:
   Signals (<=) update scheduled at the end of the simulation cycle (equivalent to non-blocking in Verilog). Variables (:=) update immediately inside a process. Misusing variables for register state often creates unexpected combinatorial feedback loops.
3. Unintended Latch Inference:
   In combinational processes, forgetting to assign a signal in every branch of an if / else or case statement forces the synthesis tool to retain the previous state, inferring a transparent latch.

Frequently asked questions