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STA path types: in2reg, reg2reg, reg2out, in2out

Every path reported by static timing analysis falls into one of four categories. The class tells you what kind of constraint applies to the path — and, more importantly, whether it is something you can fix in RTL or something the board designer has to fix outside the chip.

The four classes at a glance

Each class is named by its start and end: in for a primary input or output port, reg for a flip-flop. So in2reg means "primary input to flip-flop D", and reg2out means "flip-flop Q to primary output".

Class Start End Constrained by
in2reg Primary input Flip-flop D Input arrival time + clock period
reg2reg Flip-flop Q Flip-flop D Clock period only
reg2out Flip-flop Q Primary output Output required time
in2out Primary input Primary output External — no clock
in_a in_b FF1 reg FF2 reg logic comb FF3 reg out_y in2reg in2out (combinational) reg2reg reg2out
The four path classes shown on one design. Same flip-flops, different start and end points.

The four classes in detail

in2reg Primary input → flip-flop D

A signal arrives at a chip pin from outside, passes through some combinational logic, and lands at the D pin of a register before the next clock edge. The path has to be short enough that the external signal has time to arrive, propagate, and settle before setup.

The constraint depends on the external driver's arrival time, which RTL Bench does not know. It assumes the input is available at time 0 and reports the path delay from pin to FF.

Fix it by: registering the input at the chip boundary, or tightening the input arrival time in your constraints.

reg2reg Flip-flop Q → flip-flop D

A signal leaves a register, flows through combinational logic, and is captured by another register on the next clock edge. Both ends are inside the design, so the constraint is simply the clock period.

This is where the interesting timing work happens. The longest reg2reg path is usually the critical path — the one that determines your maximum clock frequency. If RTL Bench reports a 3.42 ns critical path on a design with a 10 ns clock, that is almost always a reg2reg path.

Fix it by: pipelining the logic (add a register in the middle), restructuring the algorithm, or giving the tools a slower clock.

reg2out Flip-flop Q → primary output

A register drives a signal that leaves the chip through a pin. The constraint is the output required time — the latest the receiving logic expects the signal to arrive.

Like in2reg, this is a chip-boundary constraint. RTL Bench reports the internal delay from the register to the pin; the external part of the constraint is not modelled.

Fix it by: inserting an output register (turning it into a reg2reg path internally and a clean reg2out of one cell).

in2out Primary input → primary output

A signal comes in through a pin, passes through combinational logic, and leaves through another pin. There is no register on the path. The clock does not constrain it — only the external timing does.

RTL Bench reports the pure combinational delay from input to output. That number is useful, but it does not tell you whether your design closes timing — it tells you how much external delay a signal accumulates in your chip.

Fix it by: putting a register in the middle. That converts in2out into in2reg + reg2out, each with its own clock-bounded constraint.

Which one to fix first

If RTL Bench reports a violation, look at the class of the worst path. The priority is:

  1. reg2reg first. This is your maximum achievable clock frequency. If it fails, the design cannot run at the target clock, period. Nothing else matters until this is fixed.
  2. in2reg and reg2out second. These depend on external constraints. Often the fix is not in the RTL but in the surrounding system — a slower clock, an extra pipeline stage at the boundary, or a relaxed input/output arrival time.
  3. in2out last. It is combinational and unconstrained by the clock. If it is slow, you have a design smell — a long combinational path with no register — but it will not break timing closure on its own.
💡 When you open the STA results page, each path is labelled with its class. Sort by slack and look at the top three classes. If the worst is in2out, your design has no registers on its critical structure — which is usually a mistake, not a signal to optimise.

Common mistakes

Optimising the wrong path

RTL Bench reports the worst path by absolute delay. If your design has an in2out path with 5 ns of delay and a reg2reg path with 4.8 ns, both are close, and both will show up in the results — but they need different fixes. Make sure you are looking at the class before you start optimising.

Treating in2out as a clock constraint

The slack number for an in2out path is computed against the same 10 ns clock period as the other classes, but that is not a real constraint. The number is only useful for comparing one combinational path against another.

Assuming in2reg means the whole path is internal

in2reg covers the internal logic from the input pin to the register, but the input signal has to arrive at the pin before that. RTL Bench does not model the arrival time — it assumes the input is available at time 0. If your upstream device has a slow output driver, the real path is longer than RTL Bench reports.

⚠️ For real signoff, you need an SDC file with explicit set_input_delay and set_output_delay constraints. RTL Bench does not read SDC — it uses a fixed 10 ns clock and assumes zero external delay. Use it for exploration, not for tape-out.

See also

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