Write and simulate VHDL in your browser

VHDL normally means installing GHDL, wiring up a Makefile, and fighting your shell before you write a single line. RTL Bench runs GHDL for you — paste an entity, click Generate, and you have a schematic and a waveform.

The smallest VHDL that does something

A 4-bit counter. Reset is active-low, the clock is 100 MHz, and the output is on q. Paste this into the editor and hit Generate.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        clk   : in  std_logic;
        rst_n : in  std_logic;
        q     : out std_logic_vector(3 downto 0)
    );
end entity counter;

architecture rtl of counter is
    signal count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, rst_n)
    begin
        if rst_n = '0' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;
    q <= std_logic_vector(count);
end architecture rtl;

What RTL Bench detects for you

There is no testbench to write and no top module to declare. When GHDL elaborates your file, RTL Bench reads the port list and drives the design automatically.

• The entity name becomes your top module. No TOP: dropdown hunting — counter is picked because it is the only entity that nothing else instantiates.
• clk gets a 100 MHz clock. Any 1-bit input whose name contains clk or clock is driven with a 50 % duty-cycle square wave.
• rst_n is treated as active-low. Held low for the first few cycles, then released. The trailing _n is what tells the simulator the polarity.

How the toolchain works

VHDL is parsed by GHDL, not by Yosys directly. RTL Bench loads the Yosys GHDL plugin, runs ghdl --std=08 -fsynopsys over your files, and hands the resulting netlist to the same schematic and STA pipeline that Verilog uses. From your side, the only difference is the file extension.

Mixing VHDL and Verilog in one project is supported — a SystemVerilog top can instantiate a VHDL entity, or the reverse. Both files go in the same upload, and the tool figures out which backend to invoke for each. See mixed-language projects for the full guide.

What does not work

GHDL is a mature tool, but the browser wrapper here has limits. These are the ones users hit most often:

• VHDL-2019 is not supported. Stick to VHDL-2008. Context declarations and conditional analysis will fail to elaborate.
• Two entities with the same name collide. Every entity in a project must have a unique identifier — GHDL treats them as global symbols.
• Unconstrained generics without defaults often fail. Give every generic an explicit default value and the elaborator will find it.
• Extended identifiers (with backslashes or spaces) are rejected. Stick to [A-Za-z_][A-Za-z0-9_]*.

Frequently asked questions