Static Timing Analysis (STA): Evaluating Silicon Delays

Functional simulation confirms that your design operates correctly in theory, but only Static Timing Analysis (STA) verifies that electrical signals arrive within setup and hold constraints across physical silicon gates.

1. The fundamentals of setup & hold constraints

In a synchronous digital circuit, data is launched from one flip-flop on a clock edge, propagates through combinational logic gates, and must settle at the receiving flip-flop before the next clock edge arrives.

T_launch + T_clk_to_q + T_comb + T_setup <= T_capture + T_clk

• T_{clk_to_q} (Clock-to-Q Delay): Time required for data to emerge at output pin Q after the clock edge triggers.
• T_comb (Combinational Delay): Total propagation time through logic gates (adders, multiplexers, NAND/NOR).
• T_setup (Setup Time): Required duration data must remain stable at input pin D before the active capturing clock edge.
• Setup Slack (S_setup): Calculated as T_required - T_arrival. Positive slack means timing closure is met; negative slack denotes a timing violation.

2. How standard-cell Liberty (.lib) lookup models work

Gate propagation delays are not static constants—they vary depending on input transition slew (t_r) and output capacitive load (C_L). Semiconductor foundries characterize standard cell libraries into 2D Non-Linear Delay Model (NLDM) lookup tables defined in the industry-standard Liberty format:

Under the hood: Pre-characterized linear delay parameters

Commercial STA engines evaluate massive 2D tables from multi-megabyte Liberty files, which can introduce noticeable file-I/O overhead in a browser environment. RTL Bench optimizes this by distilling cell timing characterizations into lightweight pre-compiled parameters: pin capacitance (cin_pf), intrinsic base delay (intrinsic_ns), and capacitive load sensitivity (load_sens_ns_per_pf):

// Example: IHP SG13G2 2-input AND gate cell parameters
"and2": {
  "drives": {
    "1": {
      "cin_pf": 0.00254,
      "intrinsic_ns": 0.07311,
      "load_sens_ns_per_pf": 2.78078,
      "fall_intrinsic_ns": 0.06426,
      "fall_load_sens_ns_per_pf": 2.23317
    },
    "2": {
      "cin_pf": 0.00255,
      "intrinsic_ns": 0.09563,
      "load_sens_ns_per_pf": 1.39782,
      "fall_intrinsic_ns": 0.08371,
      "fall_load_sens_ns_per_pf": 1.12135
    }
  }
}

Synthesizable example: Pipelined multiply-accumulate (MAC)

The following 8-bit accumulator creates a classic reg2reg critical path through an adder stage:

module mac_unit (
  input  wire       clk,
  input  wire       rst_n,
  input  wire [7:0] a,
  input  wire [7:0] b,
  output reg  [15:0] acc_out
);
  wire [15:0] mult_prod = a * b;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      acc_out <= 16'd0;
    else
      acc_out <= acc_out + mult_prod; // Critical path: register feedback adder
  end
endmodule

3. How RTL Bench executes browser-based STA

Running enterprise STA tools like Synopsys PrimeTime or Cadence Tempus requires complex TCL scripts and heavy workstation hardware. RTL Bench provides an instant timing report through an optimized cloud pipeline:

• Generic Technology Mapping: Yosys synthesizes the HDL down to generic gates (techmap -map +/techmap.v) scoped to the top-level module.
• SHA-256 Techmap Caching: Because the gate-level netlist depends only on your source and not on the chosen foundry PDK, repeat runs hit a server-side cache, evaluating in under 50ms.
• Topological Liberty Graph Traversal: The backend engine loads pre-compiled Liberty models for SkyWater 130nm, GF180, or IHP SG13G2, calculating cell propagation delays across all four path categories.

4. The four canonical path classifications

Frequently asked questions