RTL Bench PRO
Open RTL Bench →

VHDL Compilation via GHDL

Verilog and VHDL have historically been siloed. RTL Bench breaks down that wall by using GHDL to co-elaborate VHDL alongside Yosys, allowing you to mix both languages in a single project.

What is GHDL?

GHDL is the most popular open-source VHDL simulator. However, it is not just a simulator; it contains a powerful compiler that translates IEEE 1076-2008 VHDL into a format that Yosys can understand.

The Co-Elaboration Process

When you upload a .vhd file to RTL Bench, we don't just parse it as text. The backend runs:

  1. ghdl -a to analyze and syntax-check the VHDL.
  2. ghdl --synth to map the behavioral VHDL into Yosys's internal RTLIL format.
  3. Yosys takes over, optimizing the logic and mapping it to the standard cells of the target PDK.

Mixed-Language Projects

Because both VHDL and Verilog ultimately become RTLIL, RTL Bench can seamlessly instantiate a VHDL entity inside a SystemVerilog module, or vice versa. 

// SystemVerilog Top Level
module top (
    input  logic       clk,
    output logic [7:0] result
);
    // Instantiating a VHDL entity
    vhdl_counter u_counter (
        .clk(clk),
        .count(result)
    );
endmodule
⚠ Note: While GHDL handles synthesis very well, some advanced VHDL testbench constructs (like file I/O or complex access types) may not be fully supported in the web simulator.

Frequently asked questions

What happens during VHDL elaboration in GHDL?

Elaboration resolves component instantiations, computes generic parameter values, unrolls generate loops, and constructs the static execution hierarchy and signal driver nets before simulation or synthesis begins.

What is the difference between VHDL analysis and elaboration?

Analysis (ghdl -a) performs lexical, syntactic, and semantic type checking on each compilation unit. Elaboration (ghdl -e) links analyzed units together into an executable design hierarchy.

How does GHDL integrate with Yosys for synthesis?

Using the ghdl-yosys-plugin, GHDL elaborates the design and passes the instantiated hierarchy directly into Yosys internal RTLIL representation, enabling standard synthesis passes.

Next

Try it in the workbench →