RTL Bench PRO
Open RTL Bench โ†’

Simulate Verilog in your browser

Normally a Verilog simulation means installing Icarus Verilog, writing a testbench, wiring up $dumpfile and $dumpvars, and loading the result into GTKWave. RTL Bench does all of that for you โ€” click one button and the waveform appears.

Running a simulation

Open the workbench, paste any module, and click Waves in the bottom status bar. Then press โ–ถ Run Testbench. That's the entire workflow.

If your module is the counter from the VHDL guide or any design with a clock and a reset, RTL Bench auto-detects the ports and drives them. You do not need to write a testbench just to see a waveform.

What RTL Bench does for you

  • Auto-generates a testbench. Every input gets driven โ€” clocks toggle, resets pulse, and data inputs receive randomized stimulus.
  • Runs Icarus Verilog. The same open-source simulator that ships with every Linux distribution.
  • Streams back a VCD. The waveform drawer renders the value change dump directly in the browser. No GTKWave, no download, no command line.
๐Ÿ’ก If your design has no clock, RTL Bench drives every input with random values every 10 ns. Combinational designs simulate fine without a clock.

Reading the waveform

The waveform canvas shows every top-level signal as a horizontal lane. Time runs left to right, values step vertically. Click anywhere to place a cursor.

studio โ€” waveform measurement
clk 1
data_in 0x30
match_flag 0
counter 0x25
clk data match cnt A 25ns B 47ns ฮ” 22ns (45 MHz)
Click once for cursor A, again for cursor B. The header shows ฮ” and the derived frequency โ€” the fastest way to measure a clock period.

Cursor gestures

GestureWhat it does
Click the canvas Places A on the first click, B on the second, then moves whichever is nearer.
Drag a cursor Slides the cursor. Snaps to the closest signal transition.
Shift + drag Free positioning โ€” no snapping.
Hover anywhere Shows a blue hover cursor and the live value of every signal at that time.
Right-click Clears both cursors.

When you want your own testbench

RTL Bench detects a self-contained testbench by looking for $dumpvars in your source. If it finds one, that testbench is compiled and run as-is โ€” the auto-generated stimulus is skipped.

Name your testbench tb, tb_*, or *_tb so it is excluded from the top-module candidates. 

module tb;
    logic        clk = 0;
    logic        rst_n = 0;
    logic [7:0]  q;

    counter dut (.clk(clk), .rst_n(rst_n), .q(q));

    // 100 MHz clock
    always #5 clk = ~clk;

    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, tb);

        #20  rst_n = 1;   // release reset
        #500 $finish;
    end
endmodule

Two lines matter:

  • $dumpfile("waves.vcd") names the file the viewer reads. Any name works โ€” RTL Bench picks the newest .vcd in the working directory.
  • $dumpvars(0, tb) records every signal under tb and below. Passing 0 means "recurse into every scope".
โš ๏ธ If you write your own testbench and forget $finish, the simulation runs until the 30-second timeout. That's the most common reason a self-written testbench hangs โ€” always include a $finish after your stimulus.

What you don't get

Honest limitations, so you know when to reach for something else:

  • No assertions yet. SystemVerilog assert is ignored by Icarus. Use $display and check the log if you need pass/fail.
  • No coverage. The waveform is your only observation. If you need functional coverage, run a local simulator.
  • 30-second wall clock. Long-running simulations get cut off. The limit is generous for small- and medium-size designs; a large SoC test will hit it.
  • VHDL is simulated through Yosys. GHDL compiles VHDL to a netlist, then Icarus simulates that netlist. Most VHDL simulates correctly, but VHDL-specific simulation features โ€” file I/O, assert, custom resolution functions โ€” may behave differently than in GHDL directly.

Resizing the drawer

  • Drag the horizontal bar at the top of the drawer to resize it.
  • Click the ๐Ÿ—– icon to maximise โ€” the drawer fills the editor area.
  • The editor reserves space automatically, so the last lines of your source stay visible above the drawer.

Frequently asked questions

Which simulation engines are supported in RTL Bench?

RTL Bench primarily uses Icarus Verilog (iverilog) for Verilog/SystemVerilog simulations and GHDL for VHDL simulations. It also supports Verilator for ultra-fast cycle-accurate C++ co-simulation of large digital designs.

How do I zoom, pan, and measure time intervals on the waveform viewer?

You can zoom using the mouse scroll wheel or top-bar zoom buttons, click-and-drag to pan horizontally, and click anywhere to place time markers. Placing two markers automatically displays the ฮ”t time difference and equivalent frequency.

What happens if my design has an infinite loop during simulation?

Simulation execution runs inside a sandboxed container with strict execution timeouts (default 10 seconds) and memory limits. If a testbench hangs without advancing simulation time (e.g., an unclocked always @* loop), the runner gracefully aborts and flags the line.

Next

  • Timing analysis (STA) How static timing analysis complements simulation to verify circuit performance.
  • VHDL in the browser How to simulate and synthesize VHDL-2008 designs alongside Verilog.
  • Testbench guide Write self-checking testbenches with assertions and automated checks.
Try it in the workbench โ†’