FPGA Synthesis & Flashing
RTL Bench goes beyond simulation. You can synthesize your design, place-and-route it, and generate a bitstream for real hardware directly in the browser.
Supported Boards
- Sipeed Tang Nano 9K (Gowin GW1NR-9)
- Sipeed Tang Nano 20K (Gowin GW2AR-18)
- iCE40 UP5K (Lattice)
Constraint Files
To map your Verilog ports to physical pins on the FPGA, you need a constraint file. RTL Bench uses:
.cst(Gowin Physical Constraints) for Tang Nano boards..pcf(Physical Constraint File) for iCE40.
// Example .cst constraint for Tang Nano 9K
IO_LOC "clk" 52;
IO_LOC "rst_n" 4;
IO_LOC "led[0]" 10;Auto-Pin Generation
If you don't provide a constraint file, RTL Bench will attempt to auto-assign your ports to safe pins on the board. It avoids dangerous pins (like JTAG or flash pins) to prevent bricking the board.
WebSerial Flashing
Because RTL Bench is a browser tool, it uses the WebSerial API to talk to your board. This means you don't need to install any drivers or software. Simply plug in your board, click "Connect", and the tool will flash the bitstream directly.
Frequently asked questions
The flow consists of three primary stages: synthesis with Yosys (converts HDL into generic logic and maps to device primitives like LUTs and flip-flops), place and route with nextpnr (assigns logic to physical slices and routes wires), and bitstream packing (generates the binary bitstream and programs the chip).
If logic cell count exceeds available Look-Up Tables (LUTs) or routing congestion prevents legal placement, nextpnr reports an error with utilization statistics. You can inspect the schematic to optimize resource-heavy arithmetic or wide multiplexers.
Yes. RTL Bench allows you to map top-level ports to physical FPGA pins using pin constraint configuration or standard constraint files (CST for Gowin, PCF for iCE40).