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How Yosys Powers RTL Bench

Yosys is the open-source synthesis framework that acts as the engine for RTL Bench. It takes your behavioral Verilog and translates it into a structural gate-level netlist.

What is Synthesis?

When you write code like assign y = (a & b) | c;, you are describing a behavior. Silicon doesn't understand behavior; it only understands physical logic gates. Synthesis is the process of translating that behavior into actual AND, OR, and NOT gates, and deciding how they physically connect.

The Yosys Pipeline

When you hit "Generate" in RTL Bench, Yosys executes a specific sequence of passes:

  • Parsing: Yosys reads your .sv or .v file and builds an Abstract Syntax Tree (AST).
  • Elaboration (proc): It converts high-level constructs like always blocks and if/else statements into multiplexers and flip-flops.
  • Optimization (opt): It removes redundant logic, eliminates unused wires, and folds constants. (e.g., if you write 1'b1 & b, it just replaces it with b).
  • Technology Mapping (techmap): This is the final step. Yosys maps the logic to the specific standard cells provided by the PDK (like SkyWater 130nm).
💡 RTLIL: Internally, Yosys uses a format called RTLIL (RTL Intermediate Language). RTL Bench reads this RTLIL to generate the visual schematic you see on the screen.

Why Open-Source Synthesis Matters

Commercial tools like Synopsys Design Compiler cost hundreds of thousands of dollars. Yosys proves that high-quality synthesis can be done openly. RTL Bench uses Yosys because it is fast, highly scriptable, and can run directly on a web server without licensing issues.

Frequently asked questions

How does Yosys convert Verilog HDL into a logic netlist?

Yosys parses the Verilog AST, performs elaboration to create a hierarchy of internal RTLIL cells, optimizes logic using Boolean simplification passes, and maps high-level operators to target technology gates or FPGA LUTs.

What is the difference between `synth` and `synth_ice40` / `synth_gowin` in Yosys?

The generic synth command performs technology-independent logic optimization. Target-specific commands like synth_ice40 or synth_gowin execute vendor-specific mapping scripts that target device Look-Up Tables, carry chains, and flip-flops.

Can Yosys perform technology mapping to ASIC standard cell libraries?

Yes. Using the dfflibmap and abc passes with Liberty format (.lib) timing and cell definitions, Yosys maps digital logic into foundry-specific cells (like SkyWater sky130 or GF180MCU).

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