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Writing Testbenches & Auto-Segregation

A testbench (TB) is a piece of code that drives inputs into your design and checks the outputs. RTL Bench makes writing and running testbenches effortless by automatically separating them from your design files.

The Anatomy of a Testbench

Unlike your Design Under Test (DUT), a testbench does not have ports. It instantiates the DUT, generates clocks, applies stimulus, and dumps waveforms.

module tb_adder;
  // 1. Declare signals to connect to DUT
  logic [3:0] a, b;
  logic [4:0] y;

  // 2. Instantiate the DUT
  adder dut (.a(a), .b(b), .y(y));

  // 3. Apply stimulus
  initial begin
    // 4. REQUIRED: Dump waveforms for the viewer
    $dumpfile("dump.vcd");
    $dumpvars(0, tb_adder);

    a = 4'd3; b = 4'd4;
    #10; // Wait 10 nanoseconds
    
    if (y == 7) $display("PASS");
    else $display("FAIL");
    
    $finish; // End simulation
  end
endmodule

How RTL Bench Auto-Detects Testbenches

You don't need to manually configure which file is the TB. RTL Bench uses a smart regex scanner on the backend. It flags a file as a Testbench if it sees:

  • The file is named tb_*.sv or *_tb.vhd.
  • It contains $dumpvars, $dumpfile, or $finish.
  • It contains time delays like #10.
  • It contains $display, $monitor, or $error.
💡 If RTL Bench misidentifies a file, look at the file chips at the top of the editor. Files marked with a purple TB badge are excluded from synthesis and STA, but are used for simulation.

Auto-Segregation (Pasting DUT + TB together)

If you paste a massive block of code that contains both your design and your testbench, RTL Bench will automatically split them apart.

The frontend parses the text, finds the module boundaries, detects which one is the TB, and moves it to a separate virtual file. This allows the synthesizer to only look at the DUT, while the simulator looks at the TB.

Auto-Generated Testbenches

If you don't write a testbench, RTL Bench generates one for you automatically. It inspects the ports of your top module and creates a TB that:

  1. Drives the reset pin (detects active-high vs active-low).
  2. Generates a 100 MHz clock (if a clock port exists).
  3. Applies 60 cycles of random stimulus to all other input ports.
  4. Runs for 5 extra cycles to drain the pipeline.

Look at the drawer header. If it says AUTO, the simulator is using the generated TB. If it says YOUR TB, it found your custom testbench.

Frequently asked questions

What makes a testbench 'self-checking'?

A self-checking testbench compares the Device Under Test (DUT) outputs against expected golden values at each clock cycle using procedural assertions or reference models, printing an automatic PASS/FAIL result without requiring manual waveform inspection.

How does RTL Bench automatically generate testbenches for my modules?

If your file does not contain a testbench with $dumpfile, RTL Bench parses the top module port definitions, instantiates the DUT, generates clock and reset stimulus, and applies pseudo-random stimulus vectors to primary inputs.

What is the proper way to model clock generation in Verilog testbenches?

Clock generation is modeled using an initial block to set the initial state (clk = 0;) followed by an always loop with half-period delays: always #(PERIOD/2) clk = ~clk;.

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