Write and simulate Verilog in your browser

RTL Bench elaborates Verilog and SystemVerilog with Yosys — the same open-source synthesizer used by every open ASIC flow. Paste a module, click Generate, and you have a schematic, a simulation, and a timing number. No install, no Makefile, no toolchain setup.

The smallest module that does something

A 4-bit counter with an active-low reset. Paste this into the editor and click Generate.

module counter (
    input  logic       clk,
    input  logic       rst_n,
    output logic [3:0] q
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) q <= 4'h0;
        else        q <= q + 4'd1;
    end
endmodule

The always_ff block is SystemVerilog. If you prefer classic Verilog, always @(posedge clk or negedge rst_n) works too — Yosys parses both without complaint.

What Yosys accepts

Yosys is strict in some places and lenient in others. Here is what actually works in RTL Bench:

Verilog vs. SystemVerilog

RTL Bench treats both as the same language. When you click Generate, Yosys is invoked with read_verilog -sv, which accepts the SystemVerilog subset in both .v and .sv files.

That means you can write logic, always_ff, always_comb, and packed structs in a .v file and Yosys will not complain. There is no benefit to using the older Verilog-2001 syntax unless you specifically need compatibility with a local tool that rejects SystemVerilog.

Common patterns that work well

Parameterised modules

The parameter keyword makes a module reusable. Yosys elaborates each instantiation with its parameters resolved before drawing the schematic.

module reg_file #(
    parameter WIDTH = 32,
    parameter DEPTH = 16
) (
    input  logic             clk,
    input  logic             we,
    input  logic [3:0]      addr,
    input  logic [WIDTH-1:0] wdata,
    output logic [WIDTH-1:0] rdata
);
    logic [WIDTH-1:0] mem [0:DEPTH-1];

    always_ff @(posedge clk)
        if (we) mem[addr] <= wdata;

    assign rdata = mem[addr];
endmodule

Generate loops for structure

A generate for loop unrolls at elaboration. It is the clean way to write repetitive hardware without copy-paste.

genvar i;
generate
    for (i = 0; i < 8; i = i + 1) begin : gen_adder
        assign sum[i] = a[i] ^ b[i] ^ carry[i];
        assign carry[i+1] = (a[i] & b[i]) | (carry[i] & (a[i] ^ b[i]));
    end
endgenerate

RTL Bench expands this into eight separate adder cells in the schematic — each labelled with the hierarchy path so you can trace it back to the source.

Packed structs for buses

SystemVerilog packed structs are the clean way to group signals that travel together. Yosys treats them as a single wide vector.

typedef struct packed {
    logic [31:0] addr;
    logic [31:0] data;
    logic        valid;
} axi_req_t;

module sink (
    input axi_req_t req
);
    assign done = req.valid;
endmodule

What does not work

The honest limitations:

• SystemVerilog interfaces. Port lists cannot contain interface instances. Pass the signals you need, or wrap the interface as a struct.
• Assertions and covergroups. Yosys ignores them. If you want SVA checking, use a real simulator.
• Classes and OOP. SystemVerilog classes are a verification feature, not a synthesis feature. Yosys will reject them.
• real arithmetic. Only integer types are synthesizable. If you need a fixed-point multiplier, implement it with integer types.
• initial blocks that drive hardware. $dumpfile and $dumpvars work in a testbench, but initial assignments to design signals do not synthesise. Use always_ff with a reset.

How elaboration works

When you click Generate, RTL Bench runs a short Yosys script:

1. read_verilog -sv — parse every uploaded Verilog file.
2. hierarchy -top <name> — pick a top module (or auto-detect).
3. proc — flatten always blocks into logic and DFFs.
4. opt — remove dead logic and redundant cells.
5. write_json — emit the netlist the schematic renderer reads.

The whole thing runs in under two seconds for a small design. If you have many files, upload them all at once — Yosys processes them in the order you provide.

Frequently asked questions