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Setup vs. Hold Time

Static Timing Analysis (STA) verifies that every synchronous register captures valid data without timing violations. Understanding the difference between setup and hold constraints is fundamental to hardware design.

Setup Time (Max-Delay Constraint)

Setup time (T_setup) is the minimum time window data must remain stable before the active clock edge arrives. If combinational logic takes too long to propagate, the data arrives late and causes a setup violation. Setup constraints determine the maximum operational clock frequency of your chip.

Hold Time (Min-Delay Constraint)

Hold time (T_hold) is the minimum time window data must remain stable after the active clock edge has triggered. If data races ahead too quickly through a short combinational path, it corrupts the value being sampled. Crucially, hold violations are clock-frequency independent: slowing down the system clock cannot fix a hold violation!

Timing Equations & Slack

RTL Bench computes slack metrics across open PDK libraries (Sky130, GF180, SG13G2) using the following conditions: 

// 1. Setup Timing Condition (Max Delay)
// Data must arrive before clock edge + setup margin
T_cq + T_comb_max + T_setup <= T_clk + T_skew
Setup Slack = (T_clk + T_skew) - (T_cq + T_comb_max + T_setup) >= 0

// 2. Hold Timing Condition (Min Delay)
// Data must NOT change too quickly after clock edge
T_cq + T_comb_min >= T_hold + T_skew
Hold Slack  = (T_cq + T_comb_min) - (T_hold + T_skew) >= 0
⚠ Silicon Warning: While setup violations can often be mitigated in lab testbenches by reducing operating clock speed, hold violations cause chip death on real silicon. ASIC flows insert delay buffers automatically during CTS to fix hold slack.

Frequently asked questions

Can a hold time violation be fixed by decreasing the clock frequency?

No. Hold time depends only on the minimum delay along the data path compared to the clock skew between registers. Because both clock edges are the same, slowing the clock has zero effect on hold time. Hold violations must be fixed by inserting buffer delays in the data path.

Why are setup violations frequency-dependent while hold violations are not?

Setup check compares data launched on one clock edge with data captured on the next clock edge; increasing the clock period increases available time. Hold check verifies that data launched by an edge does not overwrite data captured by that same edge.

How does clock jitter and skew affect setup and hold margins?

Positive clock skew (capture clock arrives later than launch clock) helps setup time but hurts hold time. Clock jitter reduces setup margin by decreasing the effective clock period.

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