Static timing analysis in your browser
Static timing analysis answers one question: will your design meet its clock constraint? RTL Bench synthesises the design, maps it to standard cells from a real PDK, walks the longest path, and reports the number — without installing OpenSTA or a Liberty file.
Running STA
Open the workbench, paste a design, and click ⏱ Calculate STA in the bottom status bar. The button pulses while the analysis runs — usually one to three seconds for a small design.
What the numbers mean
Critical path delay
The time it takes for a signal to propagate from the start of the
longest combinational path to its end. Usually measured between two
flip-flops on a reg2reg path, but can also involve
primary inputs and outputs.
Slack
The margin between your clock period and the critical path:
slack = clock_period − critical_path_delayRTL Bench assumes a 10 ns clock period (100 MHz) by default. So a 3.42 ns critical path gives +6.58 ns slack — the design closes timing with room to spare.
| Slack | Colour | What it means |
|---|---|---|
| Positive (≥ 0) | Green | Timing closes. Design meets the clock. |
| Close to 0 | Yellow | Marginal. Any added logic will break it. |
| Negative (< 0) | Red | Violation. Design will not run at 100 MHz. |
Which PDK
RTL Bench maps your design to standard cells from one of three open-source process design kits. Every corner is TT at 25 °C; only the supply voltage and node change.
| PDK | Node | Vdd | Notes |
|---|---|---|---|
| sky130 | SkyWater 130 nm | 1.8 V | Default. Best-characterised; widest cell library. |
| gf180 | GlobalFoundries 180 nm MCU | 3.3 V | Higher voltage; good for mixed-signal and IO-heavy designs. |
| ihp | IHP SG13G2 130 nm BiCMOS | 1.2 V | Low-voltage, low-power; RF-friendly. |
Timing path classification
Every path reported falls into one of four standard categories, based on where it starts and ends. See STA path types for the full breakdown.
| Class | Start | End | What it tells you |
|---|---|---|---|
| in2reg | Input port | Flip-flop D | Setup path from an external driver. Depends on the board. |
| reg2reg | Flip-flop Q | Flip-flop D | Internal logic. Usually the critical path. |
| reg2out | Flip-flop Q | Output port | Output propagation delay. |
| in2out | Input port | Output port | Pure combinational — no clock involved. |
When you open the STA results page, each path is labelled with its class. That tells you at a glance whether the timing bottleneck is inside your design or at its boundary.
What you don't get
Honest limitations so you know when to use something else:
- Fixed corner. Only TT / 25 °C. Real signoff needs SS (slow-slow) and FF (fast-fast) corners, plus temperature and voltage variation. RTL Bench reports a typical-case estimate, not signoff.
- No setup/hold pair. Only setup analysis. Hold violations come from physical effects RTL Bench does not model.
- No clock uncertainty. Jitter, skew, and clock-tree delay are assumed to be zero. Real designs budget for them.
- Flattened netlist. STA flattens the design first. If it has many multipliers or over 50k gates after flattening, the backend times out — analyse one submodule at a time using the Top-module dropdown.
Using STA as a feedback loop
The most useful way to use STA in RTL Bench is before you commit to a design structure. Try this workflow:
- Write the simplest version of the module.
- Run STA. Note the critical path and slack.
- Pipeline the module — add a register in the middle of the critical path.
- Run STA again. The critical path should roughly halve.
- Repeat until slack is comfortably positive with margin for the tools.
This is a much faster loop than running synthesis locally. You get the number you care about — the critical path delay — in a second or two, and you can iterate on structure before writing any testbenches.
Frequently asked questions
Setup time is the minimum duration the data input must remain stable before the active clock edge. A setup violation causes the flip-flop to sample stale or invalid data, and can be resolved by slowing down the clock. Hold time is the minimum duration data must remain stable after the clock edge; hold violations cannot be fixed by changing the clock frequency and require adding delay buffers.
Slack is defined as Data Required Time minus Data Arrival Time. If arrival time exceeds required time, slack is negative. Worst Negative Slack (WNS) represents the worst timing violation across the entire netlist. A design meets timing only if WNS ≥ 0 ns.
Yes. RTL Bench allows you to view, edit, and export Synopsys Design Constraints (SDC) including create_clock, set_input_delay, set_output_delay, and set_false_path rules.