Verilog to schematic: How RTL elaboration works

Converting abstract code like always @(posedge clk) into visible wires, multiplexers, and registers is known as RTL elaboration. This guide explains how Yosys and the Eclipse Layout Kernel (ELK) turn Verilog into readable, orthogonal circuit diagrams.

1. The elaboration pipeline: HDL to RTLIL to JSON

A text editor cannot show you if an adder is connected to the wrong multiplexer branch or if a control net was accidentally left floating. RTL Bench transforms HDL into diagrams through a multi-pass compiler pipeline:

• Front-end Parsing: Yosys parses your Verilog (read_verilog -sv) or VHDL (via the GHDL plugin), verifying syntax and resolving parameters.
• Proc Pass: The proc pass translates procedural behavioral blocks (initial, always, always_comb, always_ff) into explicit multiplexer trees, priority selectors, and D flip-flops.
• RTLIL Intermediate Representation: Design elements become cells in Yosys's RTL Intermediate Language (e.g. $add, $dff, $mux, $eq).
• JSON Netlist Serialization: Yosys serializes the elaborated AST into a normalized netlist format listing ports, cell types, attributes, and bit-level connection vectors.

2. Orthogonal graph layout with ELK

Translating a netlist of cells and wires into an understandable schematic is an NP-hard graph layout problem. Without intelligent layout rules, circuits become unreadable tangles of overlapping diagonal wires.

RTL Bench uses the Eclipse Layout Kernel (ELK) with a specialized layered orthogonal routing algorithm:

Synthesizable example: Arithmetic logic unit (ALU) slice

Here is a 4-bit ALU slice demonstrating how conditional assignments synthesize into multiplexers and arithmetic logic blocks:

module alu_slice (
  input  wire       clk,
  input  wire       rst_n,
  input  wire [3:0] a,
  input  wire [3:0] b,
  input  wire [1:0] op,
  output reg  [3:0] result
);
  reg [3:0] comb_out;

  // Combinational multiplexing
  always @(*) begin
    case (op)
      2'b00: comb_out = a + b;  // Infers $add
      2'b01: comb_out = a - b;  // Infers $sub
      2'b10: comb_out = a & b;  // Infers $and
      2'b11: comb_out = a ^ b;  // Infers $xor
      default: comb_out = 4'b0000;
    endcase
  end

  // Sequential register stage
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      result <= 4'd0;
    else
      result <= comb_out; // Infers $dff
  end
endmodule

3. Vector bus collapsing & net-tracing

In modern 32-bit and 64-bit architectures, rendering every signal line individually would produce 32 parallel wires for a single addition operation.

• Vector Bus Collapsing: RTL Bench groups multi-bit nets sharing the same destination into a single thick bus line annotated with its bit width (e.g. [3:0] or [31:0]).
• Interactive Net-Tracing: Clicking on any wire, port, or pin highlights its full connection tree in bright green, tracking data fan-out across intermediate buffers and multiplexer inputs.
• Constant Folding & Inline Badges: Fixed parameters and bit-masks (such as 4'b0000) are embedded directly inside cell badges as hex labels (e.g., 0x0) to prevent dummy net clutter.

4. Coarse-grain vs. gate-level views

RTL Bench offers two distinct schematic perspectives depending on your debugging goal:

Frequently asked questions